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irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 1 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? dynamic dv/dt rating ? repetitive avalanche rated ? surface mount (irfr9110, sihfr9110) ? straight lead (irfu9110, sihfu9110) ? available in tape and reel ?p-channel ? fast switching ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 description third generation power mosfets from vishay provide the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost-effictiveness. the dpak is designed for surface mountin g using vapor phase, infrared, or wave soldering techniques. the straight lead version (irfu, sihfu series) is for through-hole mounting applications. power dissipation levels up to 1.5 w are possible in typical surface mount applications. note a. see device orientation. notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. v dd = - 25 v, starting t j = 25 c, l = 21 mh, r g = 25 ? , i as = - 3.1 a (see fig. 12). c. i sd ? - 4.0 a, di/dt ? 75 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. e. when mounted on 1" square pcb (fr-4 or g- 10 material). product summary v ds (v) - 100 r ds(on) ( ? )v gs = - 10 v 1.2 q g (max.) (nc) 8.7 q gs (nc) 2.2 q gd (nc) 4.1 configuration single s g d p-channel mosfet dpak (to-252) ipak (to-251) g d s s d g d ordering information package dpak (to-252) dpak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free and halogen- free sihfr9110-ge3 sihfr9110trl-ge3 sihfr9110tr-ge3 sihfu9110-ge3 lead (pb)-free irfr9110pbf irfr9110trlpbf a irfr9110trpbf a irfu9110pbf sihfr9110-e3 sihfr9110tl-e3 a sihfr9110t-e3 a sihfu9110-e3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 100 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 3.1 a t c = 100 c - 2.0 pulsed drain current a i dm - 12 linear dera ting factor 0.20 w/c linear derating fa ctor (pcb mount) e 0.020 single pulse avalanche energy b e as 140 mj repetitive avalanche current a i ar - 3.1 a repetitive avalanche energy a e ar 2.5 mj maximum power dissipation t c = 25 c p d 25 w maximum power dissipation (pcb mount) e t a = 25 c 2.5 peak diode recovery dv/dt c dv/dt - 5.5 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 260
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 2 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note a. when mounted on 1" square pcb (fr-4 or g- 10 material). notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --50 maximum junction-to-case (drain) r thjc --5.0 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a - 100 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma - - 0.093 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 100 v, v gs = 0 v - - - 100 a v ds = - 80 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 1.9 a b --1.2 ? forward transconductance g fs v ds = - 50 v, i d = - 1.9 a 0.97 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 200 - pf output capacitance c oss -94- reverse transfer capacitance c rss -18- total gate charge q g v gs = - 10 v i d = - 4.0 a, v ds = - 80 v, see fig. 6 and 13 b --8.7 nc gate-source charge q gs --2.2 gate-drain charge q gd --4.1 turn-on delay time t d(on) v dd = - 50 v, i d = - 4.0 a, r g = 24 ? , r d = 11 ? , see fig. 10 b -10- ns rise time t r -27- turn-off delay time t d(off) -15- fall time t f -17- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 3.1 a pulsed diode forward current a i sm --- 12 body diode voltage v sd t j = 25 c, i s = - 3.1 a, v gs = 0 v b --- 5.5v body diode reverse recovery time t rr t j = 25 c, i f = - 4.0 a, di/dt = 100 a/s b - 80 160 ns body diode reverse recovery charge q rr - 0.17 0.30 c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 3 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 4 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 5 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 6 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd - 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
irfr9110, irfu9110, sihfr9110, sihfu9110 www.vishay.com vishay siliconix s13-0168-rev. d, 04-feb-13 7 document number: 91279 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - for p-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91279 . p.w. period di/dt diode recovery dv/dt body diode forward drop body diode forward current driver gate drive inductor current d = p.w. period + - - - - + + + peak dio d e recovery d v/ d t test circuit ? dv/dt controlled by r g ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low stray inductance ? g round plane ? low leakage inductance current tran s former r g ? compliment n-channel of d.u.t. for driver v dd ? i s d controlled by duty factor d note note a. v gs = - 5 v for logic level and - 3 v drive device s v gs = - 10 v a d.u.t. l s d waveform d.u.t. v d s waveform v dd re-applied voltage ripple 5 % i s d rever s e recovery current
document number: 91344 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-252aa (high voltage) notes 1. package body sizes exclude mold flash, protrusion or gate bu rrs. mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side. 2. package body sizes determined at the outermo st extremes of the plastic body exclusive of mold flas h, gate burrs and interlea d flash, but including any mismatch between the top and bottom of the plastic body. 3. the package top may be smaller than the package bottom. 4. dimension "b" does not include dambar prot rusion. allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimens ion at maximum material condition. the dambar cannot be located on the lower radius of the foot. e b 3 l3 l4 b 2 e b d h e1 d1 a c2 l1 l2 c a1 l millimeters inches dim. min. max. min. max. e 6.40 6.73 0.252 0.265 l 1.40 1.77 0.055 0.070 l1 2.743 ref 0.108 ref l2 0.508 bsc 0.020 bsc l3 0.89 1.27 0.035 0.050 l4 0.64 1.01 0.025 0.040 d 6.00 6.22 0.236 0.245 h 9.40 10.40 0.370 0.409 b 0.64 0.88 0.025 0.035 b2 0.77 1.14 0.030 0.045 b3 5.21 5.46 0.205 0.215 e 2.286 bsc 0.090 bsc a 2.20 2.38 0.087 0.094 a1 0.00 0.13 0.000 0.005 c 0.45 0.60 0.018 0.024 c2 0.45 0.58 0.018 0.023 d1 5.30 - 0.209 - e1 4.40 - 0.173 - 0' 10' 0' 10' ecn: s-81965-rev. a, 15-sep-08 dwg: 5973
document number: 91362 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-251aa (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (dat u m a) thermal pad e1 4 d1 v ie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b 2 3 x b 3 b 4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968
application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 02-oct-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk. pleas e contact authorized vishay personnel to ob tain written terms and conditions regarding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. vishay intertechnology, inc. hereby certifi es that all its products that are identified as ha logen-free follow halogen-free requirements as per jedec js709a stan dards. please note that some vishay documentation may still make reference to the iec 61249-2-21 definition. we co nfirm that all the products identified as being compliant to iec 61249-2-21 conform to jedec js709a standards.

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